This invention relates to a method and apparatus for converting display data for use among different types of display units, and particularly to a display control method and apparatus for converting display data oriented to a CRT (cathode ray tube) display unit into display data for a display unit of a different type.
In recent years, various types of display units are used for personal computers and the like, and these include CRT display units, liquid crystal display (LCD) units and plasma display units, etc. These different types of display units are controlled differently by a host computer in displaying the same data even though the pixel arrangement is identical. To cope with this situation, there have been developed LSI devices for converting CRT display data into liquid crystal display data, as exemplified by an LSI device SED 1340F manufactured by Suwa Seikosha Co., Ltd., Japan. This LSI device is simply added to a conventional CRT display unit, and it allows CRT display data to be displayed on a LCD panel. The device temporarily stores CRT display data in its buffer memory, then converts the data into LCD display data when it reads the data out of the buffer memory. Such a data converting LSI device is useful in extensive application fields for allowing large CRT oriented display data to be displayed on a small LCD panel.
FIG. 11 shows a typical display system using the above-mentioned data converting LSI device. The arrangement includes a CRT display unit 30 which produces display signals including CRT display data 3, dot clock 2 indicating the dot period of the display data 3, and display period signal 1 indicating whether or not the display data 3 is to be displayed, a cathode ray tube (CRT) 31 on which the display data 3 is displayed, a data converter 29 which converts CRT display data into LCD display data, a LCD panel 32 having its entire screen divided into upper and lower screens where LCD upper-screen data 23 and LCD lower-screen data 24 provided by the data converter 29 are displayed, respectively, and a display data memory 21 for storing the CRT display data 3. The liquid crystal panel is technically limited in size, and a large display screen is generally constructed using two panels forming the upper and lower screens.
FIG. 12A shows the screen of CRT 31 on which the CRT display data 3 is displayed, and FIG. 12B shows the LCD panel 32 on which the LCD upper-screen display data and LCD lower-screen display data are displayed.
FIG. 13 shows in block diagram the conventional data converter 29. Shown by 4 is a timing generator which receives the display period signal 1 and dot clock 2 and produces various timing signals. For example, 6 is a segment clock signal indicating the 1-segment period made up of eight dots, 7 is a one frame end signal indicating that the CRT scanning operation for one frame has been completed, 8 is a R/W signal for setting the read mode or write mode for the display data memory 21, and 9 is a load clock signal for fetching the CRT display data 3 as a segment string. Shown by 10 is a serial-to-parallel converter which converts the CRT display data 3 in a serial form into parallel data 11 for each multi-bit segment, 12 is a write means which receives the display data 11 and produce a write address 13 and write data 14 to be stored in the display data memory 21, 16 is a read means which produces a read address 17 to retrieve data 18 from the display data memory 21 so that it is displayed on the LCD panel, and 19 is an address switching circuit which selects the write address or read address in response to a "high" or "low" state of the R/W signal 8 to provide the address signal 20 for the display data memory 21. Shown by 25 is LCD display data retrieved by the read means 16, and 22 is an LCD display data output means which receives the LCD display data 25 and produces LCD upper-screen display data 23 and LCD lower-screen display data 24.
Receiving the CRT display data 3, the CRT 31 displays segments of data in addresses "0", "1", . . . , "79", "80", "81", . . . , "7999", "8000", . . . , "15920", . . . , and "15999" sequentially from the top left to the bottom right on the screen, as shown in FIG. 12A. In contrast, the LCD panel 32 displays segments of LCD upper-screen display data 23 in addresses "0" through "7999" in the order from the top left to the bottom right of the upper screen and segments of LCE lower-screen display data 24 in addresses "8000" through "15999" in the order from the top left to the bottom right of the lower screen, as shown in FIG. 12B. It is necessary for the LCD panel 32 to receive the LCD upper-screen display data 23 and LCD lower-screen display data 24 concurrently.
Because of different manners of supplying display data to the CRT and LCD panel, the data converter 29 in conjunction with the display data memory 21 converts the CRT display data 3 into the LCD upper-screen display data 23 and LCD lower-screen display data 24. The operation of the data converter 29 will be explained in more detail. In FIG. 13, the serial CRT display data 3 is converted to units of a segment by the serial-to-parallel converter 10 to form the data 11. The converter 10 shifts the serial CRT display data 3 to align the bit position and sends out a segment of data 11 in response to the falling edge of the load clock 9 produced by the timing generator 4. Consequently, the serial CRT display data 3 is divided into segments of parallel data, and the data 11 is fed to the write means 12. The write means 12 appends a sequential address to the segment of data 11 in response to the segment clock 6, and produces the write data 14 and write address 13. The character clock 6 is a signal delayed by one clock period from the load clock 9. The write means 12 responds to the segment clock 6 to count the address, thereby producing the write address 13, while directly sending out the segment of data 11 as write data 14. The read means 16 responds to the segment clock 6 to produce the read address 17, thereby retrieving data 18 from the display data memory 21. Since the LCD panel needs to be supplied with display data for the upper and lower screens concurrently, the read address 17 is issued in such a manner that address "0" for the upper screen is produced first, which is immediately followed by address "8000" for the lower screen. The write address 13 and read address 17 are received by the address switching circuit 19 for selection in accordance with the R/W signal 8, and the selected memory address signal 20 is delivered to the display data memory 21. Namely, with the R/W signal 8 being "low", a write address 13 is given to the display data memory 21, and a portion of write data 14 is written in the display data memory 21 at the rising edge of the R/W signal 8. With the R/W signal 8 being "high", a read address 17 is given to the memory 21, and a portion of data stored in that address is read out as read data 18. The display data read means 16 latches the retrieved data 18 at the falling edge of the character clock 6 and releases it as LCD display data 25. In order to provide display data for the upper and lower screens of the LCD panel, the LCD display data output means 22 latches a portion of 8-bit LCD display data 25 as 4-bit data of address "0" in the upper screen and a 4-bit data of address "8000" in the lower screen, and then releases the data in two parts as an LCD upper-screen display data 23 and LCD lower-screen display data 24. In this manner, the CRT display data 3 is stored in the display data memory 21 by the write means 12, and it is retrieved for LCD display by the read means 16. The write and read operations take place in one segment period, i.e., 8-dot period, or 4-dot period for each operation. In consequence, the CRT display data 3 is converted into LCD display data by the data converter 29.
The foregoing prior art system implements writing and reading on one segment period, and therefore it becomes difficult to practice a large display panel for which the dot clock 2 needs to have a higher frequency. For example, a display panel of 640-by-400 dots requires a dot clock of 21 MHz (in the case of personal computer model B16/EX manufactured by Hitachi, Ltd., Japan), and the period of reading and writing is 190 ns (i.e., 1/21 MHz.times.4). In consideration of a marginal period for read/write switching, an expensive memory with access time below 100 ns is necessary. In the future, when the size of display panel expands to 720-by-512 dots, 1024-by-494 dots, 1120-by-720 dots, and even larger, the dot clock will exceed 30 MHz, and conversion to LCD data will become difficult due to the restriction of access time to memory means.